A conventional pulse width measuring device performs a counting operation in a predetermined measurement range. Accordingly, the pulse width of a signal to be measured in the predetermined measurement range can be accurately measured. However, when a signal having a pulse width outside the predetermined measurement range is input, the counter overflows, and the pulse width cannot be accurately measured.
To counter this problem, Japanese Laid-Open Patent Application No. 7-27804 discloses a pulse width measuring device that utilizes the technique of constantly setting the clock frequency of the counter at the optimum value for the pulse width of a signal to be measured.
FIG. 4 illustrates the structure of the pulse width measuring device that is disclosed in Japanese Laid-Open Patent Application No. 7-27804.
In FIG. 4, the pulse width measuring device includes a data register 3, an edge detecting circuit 6, a control circuit 7, a counter circuit 11, a selector circuit 15, and a divider 17.
In the pulse width measuring device shown in FIG. 4, the edge detecting circuit 6 detects the rise and fall of a measured signal IN, and outputs a detection signal EG1 and a detection signal EG2 to the control circuit 7. Based on the detection signals EG1 and EG2 from the edge detecting circuit 6, the control circuit 7 outputs a count enabling signal ENABLE to the counter circuit 11. The count enabling signal ENABLE is a count start/end signal for indicating the start and the end of a counting operation.
In the pulse width measuring device shown in FIG. 4, the counter circuit 11 counts a count clock signal CLK, starting from when the count enabling signal ENABLE that is output from the control circuit 7 switches to H level (the start of the counting operation) until the count enabling signal ENABLE switches to L level (the end of the counting operation). The counter circuit 11 then outputs the count value to the data register 3. The data register 3 stores and holds the count value of the counter circuit 11.
When each bit value of the counter circuit 11 changes from FFH to 00H (or when the count value overflows) in a counting operation, the counter circuit 11 shifts the count value 1 bit lower, and outputs a control signal CO to the selector circuit 15.
In the pulse width measuring device of FIG. 4, based on the count value stored in the data register 3 and the period of the count clock signal CLK, the pulse width of the measured signal IN is calculated.
The divider 17 divides a master clock signal MCLK to generate and output clock signals CLK0 through CLKn of different frequencies. Based on the control signal CO from the counter circuit 11, the selector circuit 15 selects each clock signal from the clock signals CLK0 through CLKn generated from the divider 17, starting from the clock signal of the higher frequency to the clock signal of the lower frequency. The selector circuit 17 then outputs each selected signal to the counter circuit 11 as the count clock signal CLK.
FIG. 5 illustrates the structure of the selector circuit 15 of the pulse width measuring device of FIG. 4.
Here, it is assumed that the divider 17 of FIG. 4 outputs the clock signals CLK0 through CLKn (n=3) of four different frequencies, which are obtained by dividing the master clock signal MCLK, to the selector circuit 15.
In the selector circuit 15 shown in FIG. 5, the control signal CO that is output from the counter circuit 11 of FIG. 4 is input to a counter 19 that consists of 2 bits. The counter 19 counts the control signal CO, and outputs the count value to a decoder 20.
Also, the count enabling signal ENABLE that is output from the control circuit 7 of FIG. 4 is input as a reset signal to the counter 19. When the count enabling signal ENABLE switches to the L level (the end of the counting operation), the count value of the counter 19 is reset.
Based on the 2-bit output signal from the counter 19, the decoder 20 outputs a 4-bit clock select signal to a selector 13. Among the four bits of the clock select signal, only one bit is at H level. The clock select signal is sent to one input terminal of the selector 13.
The four clock signals CLK0 through CLKn that are output from the divider 17 are input to the other input terminal of the selector 13. Based on the clock select signal, the selector 13 selects a clock signal from the clock signals CLK0 through CLKn, and outputs the selected clock signal as the count clock signal CLK.
In the selector 13 of FIG. 5, the count clock signal CLK is selected from the clock signals CLK0 through CLKn, based on the clock select signal from the decoder 20. Every time the counter 19 counts up, the decoder 20 select a clock signal from the clock signals CLK0 through CLKn, starting from the clock signal CLK0 of the highest frequency to the clock signal CLKn of the lowest frequency.
In the pulse width measuring device of FIG. 4, so as to calculate the pulse width of the measured signal IN based on the count value stored in the data register 3 and the period of the count clock signal CLK, it is necessary to obtain the period information as to the count clock signal CLK. Therefore, the selector circuit 15 of FIG. 4 stores and holds the output signal from the counter 19 as the period information as to the counter clock signal CLK in an internal register (not shown).
In the pulse width measuring device of FIG. 4, when the count value overflows in a counting operation, the counter circuit 11 halves the count value (or shifts the count value 1 bit lower), thereby doubling the period of the count clock signal CLK (or selects a clock signal with a frequency a step higher than the frequency of the previous count clock signal). Thus, the counting operation is continued.
In the pulse width measuring device of FIG. 4, however, the number of bits in the internal register for selecting the clock frequency needs to be increased, so that the counting operation is further continued even after a measured signal having a pulse width outside the predetermined measurement range is input.
Also, the number of bits in the internal register directly affects the circuit size of the pulse width measuring device of FIG. 4. If the number of bits in the internal register increases, the circuit size of the pulse width measuring device also increases, resulting in an increase in cost.